Design verification testing (DVT) is the gauntlet every power supply goes through before production. At TDK-Lambda, engineers were running these tests partly by hand: cycling units through temperature extremes (-40°C to +85°C), measuring efficiency, ripple and noise, load regulation, harmonics, inrush current, hold-up time, OCP characteristics, and dozens more parameters. A full DVT run could take the better part of a day, tying up both the test bench and the engineer.
I designed and built the system that automated the whole thing. Configure the product, set it running, come back tomorrow to a complete report. The experience of building this production system, and watching how engineers used it, is what later inspired the py-dvt-ate simulation platform.
The system controlled a full bench of instruments from over 15 manufacturers: Chroma AC sources, Kikusui and Chroma electronic loads, Lecroy and Rohde & Schwarz oscilloscopes, Vitrek power analysers, Thermotron and Espec thermal chambers, and others. Every manufacturer speaks a slightly different SCPI dialect, so I built a unified driver layer over VISA that abstracted the differences. Test code talked to clean interfaces, not raw SCPI strings with manufacturer-specific quirks baked in.
Where commercial instruments didn't exist for what we needed, I designed custom ones. Hold-up time tests required switching high-capacitance loads, and nothing on the market did this, so I built a USB-controlled capacitive load bank switch that started as an Arduino prototype and ended up as a production PCB.
Tests were plain VB.NET classes decorated with custom attributes. The framework discovered them via reflection at startup, no registration needed. It read each test's attribute metadata to determine which instruments and conditions were required, then wired everything up automatically.
Execution followed the natural structure of a DVT run: iterate through temperature groups, run each test within a group, step through every generated condition within each test. A cooperative abort mechanism let engineers safely stop a multi-hour run at any point, putting all instruments into a safe state before shutting down. That abort mechanism was unglamorous but critical; when you're driving a 3kW load at -40°C, you can't just kill the process.
This was the key to scaling across product families. Test conditions were defined as axes in XML (line voltages, load percentages, temperature points), and the framework generated the full test matrix via Cartesian product. Symbolic values like 'MinimumLineVoltage' or 'MaximumLoadCurrent' resolved against the actual product specification at runtime. The same test definition worked for a 100W single-output and a 600W quad-output without any code changes.
Multi-output power supplies have complex power budgets. A quad-output supply might have a 600W total converter limit, individual module limits of 200W each, and per-output maximums that depend on what the other outputs are drawing. The software modelled this three-level hierarchy (converter, module, per-output) and automatically distributed load across parallel electronic load channels, respecting all constraints simultaneously.
Getting this right meant the system could test worst-case load combinations that engineers would struggle to set up manually. The maths had to match what the hardware actually does; getting it wrong meant either under-testing the product or tripping protection circuits and halting the run.
After a run, the system generated reports with oscilloscope waveform captures, measurement charts, and pass/fail verdicts against specification limits. I built this on a format-agnostic element model: the report was composed as abstract elements (tables, charts, images), then rendered to Word, PDF, or HTML depending on what the engineer needed. This separation meant adding a new output format never touched the test or measurement code.
Four assemblies: a core test framework (discovery, condition generation, reporting), an instrument driver library (VISA-based, 15+ manufacturers), a functional tests assembly, and a WPF test runner. Tests were plain classes with custom attributes, discovered via reflection and automatically wired with instruments and conditions. The framework generated test matrices from XML-defined condition axes, resolved symbolic values against product specs at runtime, and modelled multi-level power derating for complex multi-output supplies.
Drove instruments from 15+ manufacturers through a unified VISA-based driver abstraction layer
Declarative test framework - tests were plain classes with custom attributes, discovered and wired up via reflection
Automatic test matrix generation via Cartesian products with symbolic value resolution against product specs
Multi-level power derating modelled the real physics: converter limits, module budgets, and per-output maximums
Data-driven configuration - new product families required only XML, no code changes
Automated report generation with oscilloscope waveform captures, charts, and pass/fail specification verdicts
Load mapping system handled multi-output supplies with parallel load channels and automatic power budget distribution
Custom instrument design (capacitive load bank switch) where commercial options didn't exist
Abstracting over 15 manufacturers' SCPI dialects taught me that 'standard' protocols are anything but. Every driver needed manufacturer-specific workarounds, and the abstraction layer was the only thing keeping test code sane.
Reflection-based test discovery was the right call. Engineers could drop a new test class into the assembly and the framework would find it, wire it up, and run it without touching any registration code.
Modelling multi-output power derating forced me to understand the physics properly. You can't fake a three-level power budget hierarchy; the maths has to match what the hardware actually does.
Running unattended overnight means every failure mode needs a safe recovery path. The cooperative abort mechanism was the most unglamorous and most important piece of the system.
This project is what made me build py-dvt-ate. Watching engineers wait for rack time to test procedure changes, I kept thinking: what if the instruments were simulated?